Modern digital systems rely on multiple clock signals to synchronize data flows through their circuits. In systems such as analog-to-digital converters (ADCs), clock timing is an important factor impacting system performance. Clock skew (i.e. the time between clock edges arriving at different circuits) must be tightly controlled in order to maximize settling time for low noise and low spurs. In digital circuits, phase noise occurs due to errors in the clock edges of the digital circuit. Phase noise in a circuit may arise from various sources. For example, fluctuations in current and temperature affect the properties of charge carriers in the conductors of the circuit and introduce random noise. Phase noise also appears as additional frequency components due to short term fluctuations that show up as side bands to the desired signal frequency. Duty cycle must also be accurately controlled for the same reasons. Moreover, given the spatial differences between the circuits that need clock signals, a clock signal generator is needed to provide control over clock skew and duty cycle.
A common solution to this control challenge is to generate clock signals off of ramp-like (triangular) waveforms. By applying direct-current (DC) thresholds to create clock edges, skew and duty control can be achieved with reasonably good precision. Another approach is to employ a Delay Locked Loop (DLL), which uses a programmable delay line and feedback to minimize skew across a device or chip. Improved performance over either of these solutions is required for many applications, however. Ramp generators can only provide from 0 to 180 degrees of edge control and are often complex circuits with many power consuming devices. And while DLLs can provide more, they do so with a very high power consumption.
Alternative systems and methods for generating clock signals in integrated circuits are desired.